1. Field of the Invention
The present invention relates to a semiconductor device provided with a step portion on a semiconductor substrate and a method of manufacturing the same, in particular, to a MOS transistor, a DRAM of a stack structure and the like and a method of manufacturing the same.
2. Description of the Related Art
As the structure of the LSI element has become finer, the gate insulting film of the MOS transistor has become thinner.
In the conventional MOS transistor, a gate electrode is formed by patterning a gate electrode film formed on a gate insulative film.
FIGS. 1A to 1D are general views of a conventional manufacturing process of a general MOS transistor, particularly, a process for processing a gate electrode.
As shown in FIG. 1A, an element separating region 101 and a gate insulative film 102 are formed on a semiconductor substrate 100. Then, a conductive film 103 is formed on the whole element separating region 101 and the whole gate insulative film 102 by means of an appropriate process such as a CVD process, as shown in FIG. 1B.
Thereafter, a resist pattern 104 is formed on the conductive film 103 by a resist coating and lithography process, as shown in FIG. 1C. The conductive film 103 is etched isotropically to form a gate electrode 105, and a metal wiring 107, using the resist pattern 104 as a mask, as shown in FIG. 1D.
However, the element separating region 101 has a step portion S, as shown in FIG. 1B. Thus, the thickness of the step portion S of the conductive film 103 is larger than the other portions, i.e., the flat portions of the conductive film 103.
Upon performing isotropic etching on a conductive film for forming a gate electrode, the etching time is selected so that the thickest portion of the conductive film 103, i.e., the step portion S of the conductive film 103 can be removed during this etching time. On the other hand, this etching time is too long to be required for removing the flat portions of the conductive film 103.
As shown in FIG. 1D, therefore, an over-etching occurs at that region of the flat portions of the conductive film 103 not masked by the resist pattern 104 and depressions 106 are formed in the substrate 100. Thus, the characteristics of the element as a MOS transistor have come to differ greatly from the designed characteristics.
This phenomenon has appeared as the gate insulative film has become thinner by making the element finer and this quick countermeasures for reducing this phenomenon has been required.
In the above-mentioned conventional MOS transistor, metal wirings (a conductive film) 107 are formed on the element separating region 101 simultaneously with formation of the gate electrode 105.
With this formation method, the upper surface of the gate electrode 105 is not flush with the metal wirings 107. When, for example, a multi-level wiring is formed, it is hard to flatten the surfaces of an inter-level film, making it difficult to pattern the upper-level wiring film.
Even if the flattering can be made easily, differences of the depths of contacts connected to the upper-level wiring film from place to place make formation of contact holes difficult. That is, the conventional method has a difficulty in making of open holes and embedding contacts.
In order to optimize the device characteristics of a DRAM (Dynamic RAM) having a stack structure, it is demanded, on one hand, that the thickness of the metal wirings, for example, be reduced at the memory cells so as to reduce a capacitance between the wirings, and it is required, on the other hand, that the thickness of metal wirings be increased at the peripheral circuit portion so as to reduce a resistance thereby to cause a large current to flow and so as to improve reliability.
In the general conventional DRAM, the metal wirings have a single thickness, and thus, it was impossible to form wirings having such thicknesses as satisfy these two contradictory requirements.
For solving this problem, there has recently been made a proposal which can change the thickness of metal wirings partially, as disclosed in Japanese Patent Kokai Publication 4-10455, for example.
Although, however, the film thickness can be changed partially with this proposal, the upper surfaces of the metal wirings are not in the same plane. Similarly to the above-mentioned MOS transistor, therefore, it is difficult to flatten the surfaces of the inter-level film when, for example, a multi-level wiring is formed.
Even if the flattering can be made easily, differences of the depths of contacts connected to the upper-level wiring film from place to place make formation of contact holes difficult.
As described above, the phenomenon has appeared as the gate insulative film has become thinner by making the element finer and this quick countermeasures for reducing this phenomenon has been required.
Further, since the upper surfaces of the gate electrode and the metal wiring are not in the same plane in the conventional semiconductor, it is difficult to pattern the upper-level wiring film and to form contact holes.